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? motorola 64k bit dynamic ram the MCM6665A is a 65,536 bit, high-speed, dynamic random- access memory. organized as 65,536 one-bit words' and fabricated using hmos high-performance n-channel silicon-gate technology, this new breed of 5-volt only dynamic ram combines high performance with low cost and improved reliability. by multiplexing row- and column-address inputs, the MCM6665A requires only eight address lines and permits packaging in standard 16-pin dual-in-line packages. complete address decoding is done on chip with addr8ss latches incorporated. data out is controlled by cas allowing for greater system flexibility. all inputs and outputs, including clocks, are fully ttl compatible. the MCM6665A incorporates a one-transistor cell design and dynamic storage techniques. ? organized as 65,536 words of 1 bit ? single + 5 v operation ( 10%) ? full power supply range capabilities ? maximum access time MCM6665A 15= 150 ns MCM6665A-20= 200 ns ? low power dissipation 302.5 mw maximum (active) (MCM6665A-15) 22 mw maximum (standby) ? three-state data output ? internal latches for address and data input ? early-write common i/o capability ? 16k compatible 128-cycle, 2 ms refresh ? ras-only refresh mode ? cas controlled output ? upward pin compatible from the 16k ram (mcm4116, mcm4517) ? fast page mode cycle time ? low soft error rate <0.1 % per 1000 hours (see soft error testing) block diagram precharge ad ~ memory cil memory -. array '0 array 8 ql ql 0 -. ci. e row decoder ~ row decoder ~ -. (5 '" memory u memory -. ! array array al a2 a3 -. 0 ~ memory memory -. array cil array "d co -. '" row decoder row decoder '" 0 ql ~ -. :g ? memory (5 memory iprecharge array u array a4 a5 a6 a? clock > * refresh function available on mcm6664a ~ ~ r-- ~ 0 u .: '" q) "iii a: ~ ~ 0 u g> e ~ ~ - -vec -vss ~ ~ ~ ~ f+ ~ write,w data in, d output data, q 2-17 MCM6665A mos in-channel, silicon-gate) 65,536-bit dynamic random access memory ad-a? d q ras cas vec vss p suffix plastic package case 648 pin assignment n/c d w ras ao a2 al vcc vss cas q a6 a3 a4 a5 a? pin names .. address input ... data in data out read/write input row address strobe column address strobe . power 1+5 v) ground this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it i~ advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high- impedance circuit. free datasheet http://www.ndatasheet.com
MCM6665A absolute maximum ratings (see note) rating symbol value unit figure 1 - output load 5v voltage on any pin relative 10 vss (except vcc) yin, vout -2 to + 7 v 9700 voltage on vcc supply relative to vss vcc -1 to + 7 v operating temperature range ta o to + 70 c storage temperature range t stg -65 to + 150 c power dissipation po 1.0 w loopf- 12ko data out current lout 50 ma note: permanent device damage may occur if absolute maximum ratings are ex- ceeded. functional operation should be restricted to recommended operating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. -includes jig capacitance dc operating conditions and characteristics (full operating voltage and temp",rature range unless otherwise noted.) recommended operating conditions parameter symbol min supply voltage vcc 4.5 vss 0 logic 1 voltage, all inputs vih 2.4 logic 0 voltage, all inputs vil -1.0- typ max unit notes 5.0 5.5 v 1 0 0 v 1 - vcc+ 1 v 1 - 0.8 v 1 -the device will withstand undershoots to the - 2 volt level with a maximum pulse width of 20 ns at the - 1.5 volt level. this is periodically sampled rather than 100% tested. dc characteristics characteristic symbol min max units notes vcc power supply current (standby) icc2 - 4.0 ma 5 vcc power supply current 6665a-15, trc=270 ns iccl - 55 ma 4 6665a-20, trc=330 ns - 50 vcc power supply current during ras only refresh cycles 6665a-15, trc = 270 ns icc3 - 45 ma 4 6665a-20, trc = 330 ns - 40 v cc power supply current during page mode cycle for tras = 10 p'sec 6665a-15, tpc=trp=145 ns icc4 - 40 ma 4 6665a-20, tpc = trp = 200 ns - 35 input leakage current (vsssvinsvcc) iiil) - 10 p.a - output leakage current (cas at logic 1, vsssvoutsvcc) 10(l) - 10 p.a - output logic 1 voltage @ lout= -4 ma voh 2.4 - v - output logic 0 voltage @ lout= 4 ma vol - 04 v - capacitance (f= 1 0 mhz t a = 25c vcc = 5 v periodically sampled rather than 100% tested) parameter symbol typ max unit notes input capacitance (ao-a?), 0 cll 3 5 pf 7 input capacitance ras, cas, write ci2 6 8 pf 7 output capacitance (q), (cas = vih to disable output) co 5 7 pf 7 notes: 1. all voltages referenced to vss. 2. vih min and vil max are reference levels for measuring timing of input signals. transition times are measured between vih and vil 3. an initial pause of 100 p.s is required after power-up followed by any 8 ras cycles beke proper device operation is guaranteed 4. current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open. 5. ras and cas are both at a logic 1. 6. the transition time specification applies for all input signals. in addition to meeting the transition rate specification, all input signals must transit between vih and vil (or between vil and vih) in a monotonic manner 7. capacitance measured with a boonton meter or effective capacitance calculated from the equation: c= ~~ 2-18 free datasheet http://www.ndatasheet.com
MCM6665A ac operating conditions and characteristics (read, write, and read-modify-write cycles) (full operil1lng voltage and temperature range unless otherwise noted; see notes 2,3,6, and figure 1) 6665a-15 6665a-20 parameter symbol min max min max random read or write cycle time trc 270 - 330 - read write cycle time trwc 280 - 330 - access time from row address strobe trac - 150 - 200 access time from column address strobe tcac - 75 - 100 output buffer and turn-off delay toff 0 30 0 40 row address strobe precharge time trp 100 - 120 - row address strobe pulse width tras 150 10000 200 10000 column address strobe pulse width tcas 75 10000 100 10000 row to column strobe lead time trcd 30 75 30 100 row address setup time tasr 0 - 0 - row address hold time trah 20 - 25 - column address setup time tasc 0 - 0 - column address hold time tcah 35 - 45 - column address hold time referenced to ras tar 95 - 120 - transition time !rise and fall) tt 3 50 3 50 read command setup time trcs 0 - 0 - read command hold time trch 0 - 0 - read command hold time referenced to ras trrh 0 - 0 - write command hold time twch 35 - 45 - write command hold time referenced to ras twcr 95 - 120 - write command pulse width twp 35 - 45 - write command to row strobe lead time trwl 45 - 55 - write command to column strobe lead time tcwl 45 - 55 - data in setup time tds 0 - 0 - data in hold time tdh 35 - 45 - data in hold time referenced to ras tdhr 95 - 120 - column to row strobe precharge time tcrp -10 - -10 - ras hold time trsh 75 - 100 - refresh period trfsh - 2.0 - 2.0 write command setup time twcs -10 - -10 - cas to write delay tcwd 45 - 55 - ras to write delay trwd 120 - 155 - cas hold time tcsh 150 - 200 - cas precharge time (page mode cycle only) tcp 60 - 80 - page mode cycle time tpc 145 - 200 - units notes ns 8,9 ns 8,9 ns 10,12 ns 11, 12 ns 18 ns - ns - ns - ns 13 ns - ns - ns - ns - ns 17 ns 6 ns - ns 14 ns 14 ns - ns 17 ns - ns - ns - ns 15 ns 15 ns 17 ns - ns - ms - ns 16 ns 16 ns 16 ns - ns - ns - 8. the specifications for trc (min), and trwc (min) are used only to indicate cycle time at which proper operation over the full temperature range 10c ~ t a ~ 70c) is assured. 9. ac measurements tt = 5.0 ns. 10. assumes that trcd~trcd (max). 11. assumes that trcd~trcd (maxi. 12. measured with a current load equivalent to 2 ttl (- 200 p.a, + 4 mal loads and 100 pf with the data output trip points set at voh = 2.0 v and vol = 0.8 v. 13. operation within the trcd (max) limit ensures that trac (max) can be met. trcd (max) is specified as a reference point only; if trcd is greater than the specified trcd(max) limit, then access time is controlled exclusively by tcac. 14. either trrh or trch must be satisfied for a read cycle. 15. these parameters are referenced to cas leading edge in random write cycles and to write leading edge in delayed write or read- modify-write cycles. 16. twcs, tcwd and trwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if twcs~twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tcwd~tcwd (min) andlrwd~ trwd (min), the cycle is read-write cycle and the data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at ac- cess time) is indeterminate. 17. tar min ~ tar = trcd + tcah tdhr min ~ tdhr = trcd + tdh twcr min ~ twcr = trcd + twch 18. toff (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels 2-19 free datasheet http://www.ndatasheet.com
MCM6665A read cycle timing trc ras vih- vil - vih- cas vil - vih- addresses vil - vih- w vil- voh_ q idata out) vol- write cycle timing trc ""r'e vih- v)l - ~ vih- vil - addresses vih - vil - vih- w vil - didataln) vih- vil - tdhr voh- q idata out! vol- highz 2-20 free datasheet http://www.ndatasheet.com
MCM6665A page mode read cycle ~-------------------------tras--------------------------------~ vih- ras vil - vih- cas vi, - vih- addresses vil - voh- o idata outl hi z ras cas w vol - page mode write cycle vih- vil - vih- vil - vih- vil-~~~~~~~-f-----1~~~~~~~-----i~~~~~f~~~~----~~~~~~~~ vih-~~~f--7\. d !data inl vi l - - ....... --i~ ~----------.=lf" 2-21 free datasheet http://www.ndatasheet.com
MCM6665A ras vih- vil - cas vih- vil - addresses vih- vil- in vih- vil- ras-onl y refresh cycle (data-in and write are don't care, cas is high) ~-------------------trc------------------~ ~--------tras----------~~ row addre~xxxxxxxxxxxxxxxxxxxxxxxxx; read-write/read-modify-write cycle ~----------------------~------trwc----------------------~------~ ~------------------------tras-------------------------~ ~ ______ ~i ~-------tar---------~1 ~-----+---------trsh----------------~ i~--------------~----~~ tcsh----------------------~ ----~~-------------tcas--------------~~ ~---------tcwd--------~ !.--tcac 2-22 toff free datasheet http://www.ndatasheet.com
MCM6665A typical characteristics i ::> f- => c.. ~ figure 2 - ras access time versus supply voltage 1.2 0,7 "- 110~trae@vee~5 v, ta~25el "" t-- _. ~ -- .- - ........ ._-_._- -- --............ ..... .............. ................... ....... .......... ~ ............ .......... ~ --~ ............. ........ ............... ............ .......... -- ~5 5~ vec, supply voltage ivol tsi figure 4 - ras access time versus ambient temperature ---- - ~~ r- ta-25c ta-ooe ~ (1.0-trae@vcc-4,5v, ta-25ci .- ~ ~ - _v ....-,-1-"'"" v a 20 40 60 80 ta, ambient temperature (oci figure 6 - ras, w input level versus supply voltage 2,5 2.0 ~ i, -~ 1.5 -- - ~ -- - --- ~ ~ vilmax- - ~ lo 0,5 ta-25c 4,5 5 5,5 vec, supply voltage (vol tsi figure 3 - cas access time versus supply voltage 1.3 ~ ~1.2 ~ ~1. 1 ::;: >= en en ~ 1.0 'i~ ~ o,g 0,8 1.2 'i'-,. ........ " (1.0-teac@vcc-5v, ta-25ci ....... , ............ ......., " .................... i'..... '!'..... ...................... ............... j-.. ta~70oe ................... ............... ~ ...................... i ~r-.. ta-25c- .... r----:: i ............... 4,5 5 5,5 vcc, supply voltage (vol tsi figure 5 - cas access time versus ambient temperature r-ta-oc ! --- (1,0-tcac@vcc-4,5v,ta-25ci ..... ~ -- v -~ ---- r"" ...--- ! 20 40 60 80 ta, ambient temperature (oci figure 7 - cas, winput level versus supply voltage 2.5 2,0 - ~- -- - -- i -- i--- - - ~max- - ~ ~ 1.5 ::> ~ 1.0 0,5 ta-25c -- 4.5 5 5.5 vee,suppl y voltage ivol tsi 2-23 free datasheet http://www.ndatasheet.com
MCM6665A typical characteristics (continued) figure 8 - iccl supply current versus cycle rate 50 ? g 40 l- i 30 >- q.. c.. :;j ei) 20 :> ~ t..> 10 t..> 50 ? g 40 l- i _ 30 >- c.. c.. :;j : 20 t; < ~ 10 50 <" g 40 l- i _ 30 >- c.. c.. ~ 20 :> t; < ~ 10 o ---,- v vcc z 5.5v ta=25c ~ i-trp-120 ns v r-" l- - 1---- ----- .... - '/ / ~ ~ k=- c-.. -~ -- f---- 2 1/trc, cycle rate imhzl figure 10 - iccl supply current versus supply voltage ta-25c ~ -- r---- f-- trp-120 ns i--"' ~ -- - --- --- -- -- - --- ~ - - - - 4.5 5 5.5 vcc, supply vol tage ivoltsi figure 12 - iccl supply current versus ambient temperature imin rasi vcc- 5.5 v - tras-160 ns f----- o 20 40 60 ta, ambient temperature loci ~ 290 ns 1- roo ns j- 1000 ns trc 290 ns roo ns 1000 ns 80 2-24 50 ? g 40 i- z a: a: b 30 >- c.. c.. :;j ~ 20 ~ ~ 10 50 ~ 40 i- z a: a: b 30 >- c.. c.. :;j ~ 20 t; < ~ 10 figure 9 - iccl supply current versus supply voltage ----- ,--- . ~ - ~ --- --~ f ... - ? taz25c - 290 ns r- tcasz 160 ns ---- i _v i - f.-- ff~ f..-- f..-- i-""" i-- i--- i--- ~ 4.5 5 5.5 vcc, supply voltage ivol tsi figure 11 - iccl supply current versus ambient temperature (min trpl vcc-5.5 v, trp-120 ns ~ ---- f-- - 1---- 1--.- f----r- 1- lqoo ns l 1 trc 290 ns --i--- 500 n.!. 1000 ns o o 20 40 60 80 ta, ambient temperature 1 ci figure 13 - icc2 supply current versus supply voltage ? g i- z a: a: :;j u >- il.. il.. :;j ei) >- MCM6665A typical characteristics (continued) 1 figure 14 - icc2 standby current versus ambient temperature vcc -15.5 v - -- -- -- -- ~ 20 40 60 ta, ambient temperature (oci -- 80 figure 16 - address input level versus supply voltage 2.5 r--r---r---~----,--- ,---- -~ f-- --- --- 1----1r---4--+----~-- ,--- - -, - - ---f---- 2.0 l----1r--+'---- '--r---- ,-- -- ---'-r-'-- -- vihmin ~~ ~ ~,~~--- ~ 1.5 i---f---i--_~-"""""=---+--+---i- --r-::: :> --i----- vilmax ~ 1.0f---~-~-+_-+_--+_-+_-+_-+_-+_~ ~ 0.5 1------if---t--+--+--t---t---t-----i--t--1 4.5 5 5.5 6.0 vcc, supply voltage (vol tsi soft error testing the storage cell depletion regions as well as the sense amplifier and its associated bit lines are susceptible to charge collection of electrons from an alpha "hit." however, the susceptibility of these vulnerable regions varies. depleted storage cells are vulnerable at all times, whereas the sense amplifiers and associated bit lines are susceptible only during the small portion of the memory cycle just prior to sensing. hence, an increase in the frequency of dynamic ram access will cause a corresponding increase in the soft error rate. to take this memory access dependency into account, the total soft error rate profile includes a cycle time component. the soft error rate due to bit line hits at the system's memory cycle rate is added to the soft error rate due to storage cell hits which are notfrequency dependent figure 18 illustrates the impact that frequency of access has on the mcm6664a/MCM6665A overall soft error rate. under normal operating conditions, the die will be expos- ed to radiation levels of less than 0.01 alpha/cm 2 /hr. ac- celerated soft error testing data is generated from at least three high-intensity sources having an alpha flux density range of 1 x 10 5 to 6 x 10 5 (alpha/cm 2 hr) placed over un- 2-25 figure 15 - icc3 supply current versus cycle rate 50 40 - -- 10 o a : vcc- 5.5 v ta-25c r-trpz 120 ns " .l"" .,.., -,-- ------ ~ -- ./ v ~", .- 2 iitrc, cycle ra te (mhzi figure 17 - data input level versus supply voltage 2.5 : 2.0 .i.. ~ -- .-- ~ --- - f-- - vilmax- - :> ~ 1.0 ~ 0.5 ta=25c 4.5 5 5.5 vee, supply voltage (voltsi coated die. figure 19 shows the soft error rate for a given alpha flux density at a cycle rate of 100 khz. the accelerated data of figures 18 and 19 project that the soft error rate for package level radiation will be less than 0.1 % / 1000 hours. system life operating test conditions 1) cycle time: 1 microsecond for read, write and refresh cycles 2) refresh rate: 1 millisecond 3) voltage: 5.0 v 4) temperature: 30 c 2 c (ambient temperature inside enclosure) 5) elevation,: approximately 620 feet above. mean sea level 6) data patterns: write the entire memory space sequential- ly with all "1"s and then perf()rm continuous sequential reads for 6 hours. next, write the entire memory space with all "o"s sequentially and then perform continuous sequentia: reads for 6 hours. next, go back to the all "1"s pattern and repeat the sequences allover again. free datasheet http://www.ndatasheet.com
MCM6665A figure 18 - accelerated soft error versus cycle time 103r-----------------------------------~ ~ 102 "" i ~ 10 " " " icellhltsl " vdd-40v 25c uncoated die ('( source: th230 3 x 105 ,,/cm 2 hr ------ -~----~---__4 " " " iblt hnehltsl " ~ 1 ~ ____ ~ ______ -l ______ ~ ____ ~ ______ ~ 10-1 10 102 103 104 cycle time i/lsi ! c:::> c:::> c:::> ~ f- ? c:: c:: a c:: c:: f- a (/) 10 7 106 105 10 4 10 3 10 2 10 10- 1 figure 19 - soft error rate versus alpha flux density f= 100 khz 25c vdd=45 v " source: th230 uncoated ole 10-2~~~~--~~--~--l-~l---~--~---j 10-3 10-2 10- 1 10 10 2 103 10 4 105 106 alpha flux density in/cm 2 hri current waveforms figure 20 - rasfcas cycle icc 50 nsf dlv time i nsl figure 22 - ras only cycle icc 50nsfdlv time insl v o ~u -80loed ii 0~ -60 ij~ >f- 40 20 ma ~c? lolo ii r, ~~ >f- ma figure 21 - long rasfcas cycle cas icc 50 nsfdlv time insl fig.ure 23 - page mode.cycle icc 50 nsf dlv time i nsl 2-26 v - 0 ~ c? ui~ -80 0 ~ uf- > 60 >u o .c colo 80 ii '::' ij f- ma -40 free datasheet http://www.ndatasheet.com
pin 14 0 pin w 3 ;d--1 r/w ~ clocks pin 4 i\.) ras r() -....j ""j)- -1 ras 1 clocks - 'in cas ~-tc:y cas i clocks i pin refresh- 1 j refresh r- 1 clocks ! ? available icm6664a ~ only i ref i add. etr ao-a? internal il row addresses iao-a61 pin numbers ,,6,7,9,10,'-1,12,13 .. i ext(lnt external 'i add. mux .. figure 24 - functional block diagram dataln l :1 buffer 1 i data out t buffer 1 1 1 of 2 data and array select row address a? i/o bus r-- +- i-- f- .... sa b192 bit array dc ... +- f-+ ... :0- 1 of 128 ~ row decode i + 8192 bit array dc .. ~ sa "0 ... ~ 0 no '0 e - ::> .. a col. dec 8192 u enable ~ sa bit array dc +- - ... .. 1 of 128 .. row decode j t 8192 add ~ sa bit array dc ~ clks r-",. ad~ ,~~~~ i i/o bus 8192 sa fot- ... dc bit array i+- ..... ... fi 10f128 ~ row decode + 8192 ... dc bit array sa f+-' .... - .. 8192 ... .... dc bit array sa ~ ... 1 of 128 ~ l .. , row decode t 8192 ~ dc bit array sa ~ pin8 ? ii vcc pin 16. ii vc:.<:, ~vbb l:j- dram s:: o s:: 0) 0) 0) (,j'i ? free datasheet http://www.ndatasheet.com
MCM6665A device initialization since the 64k dynamic ram is a single supply 5 v only device, the need for power supply sequencing is no longer required as was the case in older generation dynamic rams. on power-up an initial pause of 100 microseconds is required for the internal substrate generator pump to establish the correct bias voltage. this is to be followed by a minimum of eight active cycles of the row address strobe (clock) to initialize the various dynamic nodes internal to the device. during an extended inactive state of the device (greater than 2 ms with device powered up) the wake up sequence (8 active cycles) will be necessary to assure proper device operation. see figures 25, 26 for power on characteristics of the ram for two conditions (clocks active, clocks inactive). the row address strobe is the primary "clock" that activates the device and maintains the data when the ram is in the standby mode. this is the main feature that distin- quishes it as a dynamic ram as opposed to a static ram. a dynamic ram is placed in a low power standby mode when the device receives a positive-going row address strobe. the variation in the power dissipation of a dynamic ram from the active to the standby state is an order of magnitude or more for nmos devices. this feature is used to its fullest ad- vantage with high density mainframe memory systems, where only a very small percentage of the devices are in the active mode at anyone time and the rest of the devices are in the standby mode. thus, large memory systems can be assembled that dissipate very low power per bit compared to a system where all devices are active continuously. addressing the ram the eight address pins on the device are time multiplexed with two separate 8-bit address fields that are strobed at. the beginning of the memory cycle by two clocks (active negative) called the row address strobe and the column address strobe. a total of sixteen address bits will decode one of 'the 65,536 cell locations in the device. the column address strobe follows the row address strobe by a specified minimum and maximum time called "trcd," which is the row to column strobe delay. this time interval is also referred to as the multiplex window which gives flexibility to a system designer to set up his external addresses into the ram these conditions have to be met for normal read or write cycles. this initial portion of the cycle accomplishes the nor- mal addressing of the device. there are, however, two other variations in addressing the 64k ram: one is called the page mode cycle (described later) where an 8-bit column address field is presented on the input pins and latched by the cas clock, and the other is the ras only refresh cycle (described later) where a 7-bit row address field is presented on the in- put pins and latched by the ras clock. in the latter case, the most significant bit on row address a7 (pin 9) is not re- quired for refresh. see bit address map for the topology of the cells and their address selection. normal read cycle a read cycle is referred to as normal read cycle to differen- tiate if from a page-mode-read cycle, a read-while-write cycle, and read-modify-write cycle which are covered in a later section. the memory read cycle begins with the row addresses valid and the ras clock transitioning from vih to the vil level. the cas clock must also make a transition from vih to the vil level at the specified trcd timing limits when the column addresses are latched. both the ras and cas clocks trigger a sequence of events which are controlled by several delayed internal clocks. also, these clocks are linked in such a manner that the access time of the device is in- dependent of the address multiplex window. the only stipulation is that the cas clock must be active before or at current waveforms vee icc figure 25 - supply current versus supply voltage during power up, ras, cas=vcc v ma vee icc 2-28 figure 26 - supply current versus supply voltage during power up, ras, cas=vss i . . . - ---+----"t- * iiili i i i v 10 ma -5 free datasheet http://www.ndatasheet.com
MCM6665A the trcd maximum specification for an access (data valid) from the ras clock edge to be guaranteed (trac). if the trcd maximum condition is not met. the access (tcac) from the cas clock active transition will determine read ac- cess time. the external cas signal is ignored until an inter- nal ras si~nal is available, as noted in the functional block diagram, figure 24. this gating feature on the cas clock will allow the external cas signal to become active as soon as the row address hold time (trah) specification has been met and defines the trcd minimum specification. the time dif- ference between trcd minimum and trcd maximum can be used to absorb skew delays in switching the address bus from row to column addresses and in generating the cas clock. once the clocks have become active, they must stay active for the minimum (tras) period for the ras clock and the minimum (tcas) period for the cas clock. the ras clock must stay inactive for the minimum (trp) time. the former is for the completion of the cycle in progress, and the latter is for the device internal circuitry to be precharged for the next active cycle. data out is not latched and is valid as long as the cas clock is active; the output will switch to the three-state mode when the cas clock goes inactive. the cas clock can re- main active for a maximum of 10 ns (tcrp) into the next cycle. to perform a read cycle, the write (w) input must be held at the vih level from the time the cas clock makes its active transition (trcs) to the time when it transitions into the inactive (trch) mode. write cycle a write cycle is similar to a read cycle except that the write (w) clock must go active (vil leved at or before the cas clock goes active at a minimum twcs time. if the above condition is met, then the cycle in progress is referred to as a early write cycle. in an early write cycle, the write clock and the data in is referenced to the active transition of the cas clock edge. there are two important parameters with respect to the write cycle: the column strobe to write lead time (tcwl) and the row strobe to write lead time (trwl). these define the minimum time that ras and cas clocks need to be active after the write operation has started (w clock at vil leved. it is also possible to perform a late write cycle. for this cycle the write clock is activated after the cas goes low which is beyond twcs minimum time. thus the parameters tcwl and trwl must be satisifed before terminating this cycle. the difference between an early write cycle and a late write cycle is that in a late write cycle the write (w) clock can occur much later in time with respect to the active transition of the cas clock. this time could be as long as 10 microseconds - [trwl + trp + 2ttl. at the start of a write cycle, the data out is in a three-state condition and remains inactive throughout the cycle. the data out remains three-state because the active transition of the write (w) clock prevents the cas clock from enabling the data-out buffers as noted in functional block diagram. the three-state condition (high impedance) of the data out pin during a write cycle can be effectively utilized in a system that has a common input/ output bus. the only stipulation is that the system use only early write mode operations for all write cycles to avoid bus contention. 2-29 read-modify-write and read-while-write cycles as the name implies, both a read and a write cycle is ac complished at a selected bit during a single access. the read- modify-write cycle is similar to the late write cycle discussed above. for the read-modify-write cycle a normal read cycle is in- itiated with the write (w) clock at the vih level until the read data occurs at the device access time (trac). at this time the write (w) clock is asserted. the data in is setup and held with respect to the active edge of the write clock. the cycle described assumes a zero modify time between read and write. another variation of the read-modify-write cycle is the read-while-write cycle. for this cycle, the following parameters (trwd, tcwd) play an important role. a read- while-write cycle starts as a normal read cycle with the write (w) clock being asserted at minimum trwd or minimum tcwd time, depending upon the application. this results in starting a write operation to the selected cell even before data out occurs. the minimum specification on trwd and tcwd assures that data out does occur. in this case, the data in is set up with respect to write (w) clock active edge. page-mode cycles page mode operation allows faster successive data opera- tions at the 256 column locations. page access (tcac) is typically half the regular ras clock access (trac) on the motorola 64k dynamic ram. page mode operation consists of holding the ras clock active while cycling the cas clock to access the column locations determined by the 8-bit column address field. there are two controlling factors that limit the access to all 256 column locations in one ras clock active operation.-these are the refresh interval of the device (2 ms/128= 15.6 microseconds) and the maximum active time specification for the ras clock (10 microseconds). since 10 microseconds is the smaller value, the maximum specification of the ras clock on time is the limiting factor of the number of sequential page accesses possible. ten microseconds will provide approximately (10 micro- seconds/ page mode cycle time) 50 successive page accesses for every row address selected before the ras clock is reset. the page cycle is always initiated with a row address being provided and latched by the ras clock, followed by the column address and cas clock. from the timing illustrated, the initial cycle is a normal read or write cycle, that has been previously described, followed by the shorter cas cycles (tpc). the cas cycle time (tpc) consists of the cas clock active time (tcas), and cas clock precharge time (tcp) and two transitions. in addition to read and write cycles, a read- modify-write cycle can also be performed in a page mode operation. for a read-modify-write or read-while-write type cycle, the conditions normal to that mode of operation will apply in the page mode also. the page mode cycles il- lustrated show a series of sequential reads separated by a series of sequential writes. this is just one mode of opera- tion. in practice, any combination of read, write and read- modify-write cycles can be performed to suit a particular application. refresh cycles the dynamic ram design is based on capacitor charge storage for each bit in the array. this charge will tend to free datasheet http://www.ndatasheet.com
MCM6665A degrade with time and temperature. therefore, to retain the correct information, the bits need to be refreshed at least once every 2 ms. this is accomplished by sequentially cycling through the 128 row address locations every 2 ms, or at least one row every 15.6 microseconds. a normal read or write operation to the ram will serve to refresh all the bits (256) associated with that particular row decoded. ras only refresh - when the memory component is in standby the ras only refresh scheme is employed. this refresh method performs a ras only cycle on all 128 row addresses every 2 ms. the row addresses are latched in with the ras clock, and the associated internal row locations are refreshed. as the heading implies, the cas clock is not re- quired and should be inactive or at a vih level to conserve power. pin assignment comparison vbb vss n/c vss refresh vss d cas d cas d cas w 0 w 0 w 0 a6 a6 ras a6 ao a3 ao a3 ao a3 a2 a4 a2 a4 a2 a4 al a5 a1 a5 a1 a5 vdd vec vcc n/c vce a7 mcm6633a mcm6664a MCM6665A n/c vss refresh vss n/c vss d cas d cas d cas w 0 w 0 w 0 a6 a6 a6 ao a3 ao a3 ao a3 a2 a4 a2 a4 a2 a4 al a5 a1 a5 al a5 vcc a7 vcc a7 vcc a7 pin variations pin number mcm4116 mcm4517 mcm6632a mcm6663a mcm6664a MCM6665A 1 vbbi-5vi n/c refresh n/c refresh n/c 8 vddi + 12 vi vcc vcc vcc vcc vcc 9 vcci+5vi n/c a7 a7 a7 a7 2-30 free datasheet http://www.ndatasheet.com
MCM6665A ~ -5 ~ ~ a:: ~ MCM6665A bit address map row address a7 a6 a5 a4 a3 a2 al ao column address a7 a6 a5 a4 a3 a2 al ao row pin 8 0 hex fe ff fe fd fa fb fb f9 column addresses oec a7 a6 a3 a4 as a2 ao al 254 0 255 252 253 250 251 248 249 ~ ~------------------------~------------------------.---+~--~~------~---------- ~ ~ "0 u 00 88 ~uju.. :x:u..u.. ~~:il ann ~o~ ~~~ s::c;8 o;:;oe; ~ "" g;)88;g388c;8 2-31 42 43 40 41 3f 3e 3d 04 03 02 01 00 66 67 64 65 63 62 61 o o o 0 o 0 o 0 o 0 o 0 o 0 o 0 data stored= din $ aox $ al y column address al o o row address ao o data stored true inverted o inverted. true free datasheet http://www.ndatasheet.com

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